Decreasing the size of completed device packages is an ongoing design goal in the field of semiconductor device manufacture. The electronics industry has moved from decreasing the size of packages which include a single semiconductor die (chip) to miniaturization of packages which include a plurality of chips within the same package.
For example, a “package on package” or “PoP” device can include a memory die connected with bond wires to a first substrate, and a logic die connected with bond wires to a second substrate. The first substrate can provide circuit routings (i.e. electrical traces or trace routings) and a low-density ball grid array (BGA) for connection of the memory die to the logic die, while the second substrate can provide circuit routings and a high-density BGA for connection of the logic die to a receiving substrate such as a motherboard. The BGA of the first substrate is attached to landing pads on an upper side of the second substrate. Thus the memory die can be stacked on, and electrically connected to, the logic die with short electrical connections which decreases signal delay between the two dies. Further, each die can be tested prior to assembly to insure functionality, thereby reducing scrap and rework.